The present invention relates generally to a system for generating an oscillator signal and, more particularly, to a phase-locked loop (PLL) for generating an oscillator signal.
A phase-locked loop (PLL) generates an oscillator signal having a constant phase relationship with an input reference signal. PLLs are widely used in various applications such as radio, telecommunications, computers, and other electronic applications. A PLL includes a voltage-controlled oscillator (VCO) for generating the oscillator signal based on a control voltage, and a phase detector for comparing the phase of the oscillator signal with that of the input reference signal and for generating an error signal based on the detected phase difference. The PLL also includes a loop filter for filtering the error signal and generating the control voltage used by the VCO. External calibration circuits may be used for calibrating the VCO.
Generally, PLL systems are expected to operate over a wide range of frequencies and over a wide range of process, voltage and temperature (PVT) variations. For stable operation, the bandwidth of the PLL is required to be dependent only on the frequency of the input reference signal. However, the bandwidth may vary with various other parameters, such as process, voltage and temperature (PVT) variations, loop division factor ‘N’, PLL design parameters and the like. These parameters introduce undesired variance into the PLL bandwidth and degrade the loop stability of the PLL. To stabilize the bandwidth, input reference signal frequency may be tracked using a dual charge pump circuit in PLLs. A detailed description of one such above mentioned PLL system has been provided below in conjunction with FIG. 1.
Referring now to FIG. 1, a schematic diagram illustrating a conventional PLL 100 is shown. The PLL 100 includes a VCO 102, a frequency divider 104, a phase detector 106, a dual charge pump circuit 108, an active loop filter 110, a calibration circuit 112 and a reference current generation circuit 114. The VCO 102 generates an oscillator signal based on a control voltage. The phase detector 106 is connected to the VCO 102 by way of the frequency divider 104 and compares the phase of the oscillator signal with that of an input reference signal (fref) and generates an error signal based on the detected phase difference. The frequency divider 104, which is connected between the VCO 102 and the phase detector 106, provides a fraction of the oscillator signal to the phase detector 106. The dual charge pump circuit 108 is connected to the phase detector 106 and the VCO 102. The dual charge pump circuit 108 receives the VCO current from the VCO 102 and generates two charge pump currents using the error signal and according to a predetermined ratio. The active loop filter 110, which is connected between the dual charge pump circuit 108 and the VCO 102, receives the two charge pump currents and generates the control voltage, which is then provided to the VCO 102. A fraction of a reference current generated by the reference current generation circuit 114 is provided to a transconductance stage (not shown) within the active loop filter 110 as a bias current. The bias current is used to bias the transistors within the transconductance stage.
The calibration circuit 112 is connected to the VCO 102 and coarse tunes the VCO 102 close to a locking frequency, while keeping the PLL 100 in an open loop. Thereafter, the VCO 102 is fine tuned to the locking frequency by closing the loop. The predetermined ratio between the two charge pump currents is adjusted to optimize the bandwidth of the PLL 100 and the bandwidth is made directly proportional to the input reference frequency.
The conventional PLL 100 is a self-biased PLL and the bandwidth of such a self-biased PLL remains stable. However, the loop dynamics of a self-biased PLL may be affected by unwanted changes in the DC gain and the zero location of the PLL. Such unwanted changes are introduced due to a change in transconductance by the transconductance stage. For example, the transconductance may change with a change in the value of a poly-resistor used in reference current generation circuit 114. The value of the poly-resistor may vary with the change in the process and temperature variations. The bias current generated by the reference current generation circuit 114 depends on the value of the poly-resistor and thus any variation in the poly-resistor value causes a fluctuation in the bias current that translates into variations in the transconductance at the transconductance stage. The DC gain and the zero location of a self-biased PLL are proportional to the transconductance and vary with the variations in the transconductance and further degrade the loop dynamics of the self-biased PLL.
It would be advantageous to have a PLL that compensates for variations in the DC gain and zero location. It also would be advantageous to have a PLL with improved loop dynamics.